1. Technical Field of the Invention
The present invention relates to synchronizing multiplexers, and particularly to a method and apparatus for synchronizing multiple-stage multiplexers.
2. Description of Related Art
A multiplexer is a device that combines multiple streams of data into a single, higher speed stream of data. Some multiplexers can be viewed as parallel-to-serial converters. An N:1 multiplexer, shown in FIG. 1, receives N streams of input data at a data rate R and generates a stream of data at data rate N*R. A simplified block diagram of the N:1 multiplexer is illustrated in FIG. 2. An input register stores a bit value from each input data stream in parallel. A selector switch is connected between the output of each bit from the input register and the output of the N:1 multiplexer. An N-state counter cycles through N different counter states. The output of the counter drives a control input of the selector switch. In this way, the selector switch sequentially connects the output of the N:1 multiplexer to the output of each bit from the input register. For exemplary purposes only, the order of connection to the multiplexer output is from the top bit of the input register to the bottom bit thereof, as shown in FIG. 2. The carry output of the N-state counter drives the clock input of the input register. For an input data rate R, the clock frequency of the N-state counter is N*R and the clock frequency of the input register is R.
For reasons of practicality, multiplexers are typically implemented using smaller sized multiplexer circuits. FIG. 3 is a block diagram of an implementation of a multiple-stage multiplexer. The multiple-stage multiplexer employs, in a first stage, N M:1 multiplexer circuits or sub-multiplexers that operate in parallel at input data rate R. In a second stage, a single N:1 multiplexer circuit receives the output of each M:1 multiplexer circuit at input data rate M*R. The output of the N:1 multiplexer circuit has a data rate of M*N*R.
In the multiple-stage multiplexer illustrated in FIG. 3, the multiplexer circuits in the first stage must be synchronized with each other so that the data generated by the multiple-stage multiplexer is in a predictable order. The multiplexer circuits in the first stage are synchronized when the N-state counters therein are all in the same state. FIG. 4 illustrates the multiple-stage multiplexer generating the correct ordering of output bits when the multiplexer circuits are synchronized with each other. In contrast, FIG. 5 illustrates the multiple-stage multiplexer when a multiplexer circuit in the first stage thereof is not synchronized with the other multiplexer circuits.
When power is first applied to a multiple-stage multiplexer, the internal (N-state) counters initially assume random states. Consequently, the multiplexer circuits in the first stage of a multiple-stage multiplexer will not be initially synchronized with each other. A conventional approach for synchronizing the internal counters in a multiple-stage multiplexer implements the internal counters with reset capability so that the internal counters may be reset simultaneously with a single reset signal This conventional synchronization approach, however, requires that the reset signal have relatively precise timing for each internal counter in order to comport with necessary set-up and hold times relative to the clock signal applied to the internal counters. In instances in which the multiplexer circuits in the first stage are implemented in more than one integrated circuit chip, the conventional synchronization approach becomes less effective as speeds increase.
Another prior synchronization approach places the multiplexer circuits of a multiple-stage multiplexer in random states until the carry output signals generated by the internal counters occur at the same time. The multiplexer circuits may be placed in random states by, for example, connecting the reset input of each multiplexer circuit to a pseudo-random pulse generator, as shown in FIG. 6. By resetting the multiplexer circuits at pseudo-random times, the multiplexer circuits are effectively placed in pseudo-random states. Alternatively, the multiplexer circuits may be placed in random states by temporarily powering down each multiplexer circuit at the same time. Circuit breaker type circuits may be utilized to temporarily power down the multiplexer circuits, as shown in FIG. 7. A shortcoming with this prior synchronization approach, however, is that the carry output signals generated by the multiplexer circuits are substantially slower relative to the frequency of the clock input of the internal counters. The carry output signals thus lack the timing precision necessary to accurately determine whether the carry output signals are generated during the same period of the internal counter clock.
Other prior synchronization techniques utilize built-in-test-equipment (BITE) for applying test patterns to the multiple-stage multiplexer and monitoring the value of each bit in the output generated by the multiple-stage multiplexer. As the output data rate of the multiple-stage multiplexers increases, more sophisticated BITE must be utilized in order to monitor the bit values generated by the multiple-stage multiplexers. Sophisticated BITE is undesirable because it is expensive.
Based upon the foregoing, there is a need for synchronizing multiplexers in a relatively accurate and inexpensive manner.